Senior Staff Timing Engineer - 2101250
Marlborough, MA  / Morrisville, NC 
Posted 8 days ago
Job Description
About Marvell

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world's leading technology companies for 25 years, we move, store, process and secure the world's data with semiconductor solutions designed for our customers' current needs and future ambitions. Through a process of deep collaboration and transparency, we're ultimately changing the way tomorrow's enterprise, cloud, automotive, and carrier architectures transform-for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It's what's keeping the world connected, businesses running, and information flowing. If you're ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

The Opportunity

As part of the Infrastructure Processors physical design team, you will be designing next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G, and networking applications. Our team consists of individuals who develop cutting-edge methodology and implement block-level and partition-level designs. Come join a world-class team and help bring the next generation of exciting products to market!

Job Responsibilities:

Strong user of Synopsys PrimeTime (or other equivalent timing tool) including these skills:

  • translating design timing requirements into SDC
  • accurate evaluation of PrimeTime timing reports to identify solutions to timing issues
  • extracting relevant timing data from timing runs interactively
  • Strong knowledge on several key static timing analysis concepts which can include crosstalk analysis, timing of I/O interfaces, statistical modeling, scan timing, global clock balancing, etc.
  • Strong scripting skills in Tcl and Perl. Python also desired.
  • Experience in developing, supporting or contributing to chip-level timing flow definition.
  • Experience with ASIC or processor-style design flow and timing closure.
  • Overall knowledge of RTL to GDSII flow and issues which can impact timing.
  • Proven track records of executing chip or partition level timing analysis and closure activities and taping out complex SOC chips under tight schedule pressure.
  • Experience with interacting with multiple disciplines to resolve design/timing issues is a plus.
  • Understanding of current design technologies used in major foundries is desired.
  • Detail oriented, self-motivated team worker with good verbal and written communication skills.



Bachelor's degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience.
Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience.

The Perks

With competitive compensation and great benefits, you will enjoy our workstyle within an incredible culture. We'll give you all the tools you need to succeed so you can grow and develop with us. For additional information on what it's like to work at Marvell, visit our page.

Your Future

Marvell provides a work environment that promotes employee growth and development. We are searching for an individual who wants to grow with the company and will strive to improve performance. If you are driven, personable, and energetic, there will be additional opportunities for you here at Marvell.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at or 408-222-3604.


Job Summary
Start Date
As soon as possible
Employment Term and Type
Regular, Full Time
Required Education
Bachelor's Degree
Required Experience
15+ years
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